6800 CL32 with 2x32 GiB A-die
I had to manually change ODT settings to pry open a window of stability with regard to voltages. I did manually tune all ODT settings except CA ODT and CK ODT which i left to auto.
ram: F5-6000J3238G32GX2-TZ5K
Motherboard: msi pro z790-p wifi DDR5
Bios version: AD3
DRAM VDD: 1.4
DRAM VDDQ: 1.4
CPU VDD2: 1.39
CPU VDDQ: 1.25
CPU SA: 1.155
CPU PLL SFR voltage: 1.020
RING PLL SFR voltage: 1.005
SA PLL SFR voltage: 0.975
E-core L2 PLL SFR Voltage: 0.990
MC PLL SFR voltage: 1.02
DRAM VPP Voltage: 1.77
BLCK 100MHz Lock On: enabled
Memory Fast Boot: Slow Training
Training Mode: Intel MRC
Early Write Time centering 2: Enabled
Early DIMM DFE Training: Disabled
Write Timing Centering 1D: Disabled
Write Voltage Centering 1D: Disabled
Early Read Time Centering 2D: Disabled
TxDQ TCO Comp Training: Disabled
Read Timing Centering 1D: Disabled
Read Voltage Centering 1D: Enabled
Command Voltage Centering: Enabled
VccDLL Bypass Training: Enabled
Early Command Voltage Training: Enabled
Late Command Training: Disabled
Clock TCO Comp Training: Enabled
CMD CTL Drive Strength / Tx Equ: Disabled
CMD CTL CLK Slew Rate Training: Disabled
CMD/CTL Drive Strength Up/Dn 2D: Disabled
DIMM RON Training: Enabled
DIMM ODT Training: Enabled
Write Drive Strength/Equalization 2D: Disabled
Read Equalization Training: Enabled
DIMM DFE Training: Enabled
Read ODT Training: Disabled
Write Slew Rate Training: Enabled
PanicVttDnLp Training: Enabled
Read Vref Decap Training: Enabled
Vddq training: Disabled
Comp Optimization Training: Enabled
Read Amplifier Training: Enabled
Tx DQS DCC Training: Enabled
Write Voltage Centering 2D: Enabled
Read Voltage Centering 2D: Enabled
Receive Enable Centering 1D: Disabled
Round Trip Latency: Enabled
Read Timing Centering 1D JR: Disabled
Turn Around Timing Training: Disabled
Rank margin tool: Enabled
Rank margin tool per bit: Disabled
Write DQ/DQS retraining: Disabled
Write0 training: Disabled
Row Hammer Prevention: Disabled
Margin Limit Check: Disabled
Memory Test: Disabled
Memory Bandwidth Enhanced: [Mode 4]
A.I. Training Mode: [Mode 2]
A.I. Payload Enhance Mode: [Mode 8]
VTT ODT: [Enabled]
Enhanced Interleave: [Enabled]
ODT finetune: [2]
rttwr: 34
rttnomrd: 40
rttnomwr: 40
rttpark: 34
rttparkdqs: 34
CA ODT (CHA/D0/GA): 480
CA ODT (CHA/D0/GB): 240
CA ODT (CHA/D1/GA): 240
CA ODT (CHA/D1/GB): 120
CA ODT (CHB/D0/GA): 480
CA ODT (CHB/D0/GB): 240
CA ODT (CHB/D1/GA): 240
CA ODT (CHB/D1/GB): 120
Read ODT Duration: 5
ODT read delay: 2 (auto setting)
ODT Write Duration: 6
ODT Write Delay: 0
Code:
tCL 32
tRCD 40
tRCDw 16
rRP 32
tRAS 32
tRFC2 584
tRFCPB 424
tREFI 65528
tWR 60
tWR_MR 96
tWTR 8
tWTR_L 12
tRRD 8
tRRD_L 10
tRTP 12
tRTP_MR 12
tFAW 32
tCWL 16
tCKE 8
tCCD 8
tCCD_L 16
tCCD_L_MR 16
tRDRDSG 16
tRDRDDG 8
tRDRDDR 12
tWRWRSG 16
tWRWRDG 8
tWRWRDR 16
tRDWRDG 22
tRDWRDG 22
tRDWRDR 20
tWRRDSG 64
tWRRDDG 54
tWRRDDR 16
tWRPRE 64
tRDPRE 16
tXP 8
tXPDLL 16
tPRPDEN 2
tRDPDEN 8
tWRPDEN 12
tCPDED 16
tREFIx9 255
tXSDLL 8132
tMOD 52
tZQCS 114
tZQCAL 512
tXSR 256
tREFSBRD 106
tCSH 42
TCSL 8
tCA2CS 8
tCKCKEH 12
tRFM 292
RTL init values: 68, 66
DQ ODT Vref Dn: 10
CMD Drv Vref Dn: 5
CTL Drv Vref Dn: 8
CLK Drv Vref Dn: 5
VDD swtiching Frequency: 1250 Khz
VDDQ swtiching Frequency: 1500 Khz
VDD swtiching Frequency: 1000 Khz
https://www.youtube.com/watch?v=zC8D8rUjWqU
Ran out of memory when running mprime large FFT which is why the test was ended early. I considered running it again later but didn't see a point in bothering with that, at least not yet.